Blog entry

What’s all the fuss about two dimensional materials?

By Mario Ribeiro (CIC-Nanogune)

In the last decade, two dimensional materials have been the target of intense study and interest by both researchers and companies alike. A great share of publications on high impact factor journals is related to this hot-topic, and companies, particularly in the electronics field, are quickly introducing these new materials in their activity roadmaps. It’s unusual for industry and research to walk so closely together in a field that emerged so recently. Why is it then that two dimensional materials drive so much interest from these communities?  To understand why, let’s travel back to the year 2004.

By then, major electronic powerhouses were introducing 40 nm planar ultrathin body gate transistor technologies to the market. The roadmaps lead them to even smaller devices, with International Technology Roadmap for Semiconductors (ITRS) projections pointing towards 10 nm in a not so far future, as seen in Figure 1. Their goals: high performance, low power consumption, low foot-print (flexible if possible) devices; all at lower costs. The driving concept was integrating more transistors in devices with smaller foot-print to enable new applications. Achieving this integration density required (and still does) the use of expensive fabrication techniques to deposit homogenous high purity thin films on large scale, to “print” millions of nanometer sized features using lithographic techniques in ultraclean environments, and “process flows” with dozens of steps where reliability, repeatability, and reproducibility are all main concerns. Production yield dictates the company profit.  And not only have the roadmaps revealed what the industry desired, but they also identified  the technological concerns that needed to be addressed, as reducing “short-channel” effects, decreasing leakage currents, increasing ON/OFF ratios, using performance boosters as high mobility channels and high k- dielectrics, and lowering subthreshold swings.  All of these are connected to the figures of merit used to assess the performance of transistors.

Figure 1 – Transistor technology trends and perspectives, as summarized in the 2007 annual review of ITRS. Gate length and half-pitch of metal lines in Flash, dynamic random-access memory (DRAM), and microprocessor unit (MPU) products.

As a quick overview on transistors you can say that they work by modulating (enhancing or lowering) the conductivity of a channel connecting two (metal) contacts, drain and source. The channel then transports more or less charge current under the same source-drain bias via this modulation. In the so called metal-oxide-semiconductor field effect transistors (MOSFETs), the channel is separated from a third metal contact using a dielectric (usually an oxide). Applying a bias between this contact (gate) and the channel will drive mobile free carriers from the source-drain contacts to the channel. As you increase the gate bias, the carrier density in the channel near the interface will increase, effectively increasing its conductivity. You will end up with the possibility of labeling as ON and OFF the high and low current states that you control with your gate, and as “threshold” the device onset. High ON/OFF current states provide the Boolean logic through which computers are programmed. Figure 2 depicts a p-type planar body MOSFET.

Figure 2 – Standard p-type body MOSFET design.  n+pn+ bipolar junction connecting two metal contacts, drain and source. The gate will induce by field effect an inversion layer in the p-type channel, effectively turning it n-type close to the interface with the oxide. The transport across this device will happen mainly by the majority carriers (electrons in this case).

Where do two dimensional (2D) materials fit in? As a multi-million dollar company using top-end technology to miniaturize devices, you want to have as many transistors as possible in the least possible space to perform large amounts of computations in small and portable everyday gadgets. To keep up with the roadmap, you decrease the size of the transistor, but at some point the channel length becomes so small that electrons tunnel from the drain to source metal electrodes. You will no longer have the same ON current, and your OFF currents will increase. Also, having the drain and source contacts too close will couple them electrostatically, and the bias you apply on one will affect the energy barrier at the other contact, lowering it, increasing the “OFF” state current, also called “drain-induced barrier lowering”. To lower the parasitic contact resistance, the areas underneath the metals are heavily doped via ion implantation, effectively creating a npn or pnp bipolar junction transistor (BJT) channel. When biasing the channel (if it is too thick), the np junctions depletion layers will “punchthrough” each other, providing a pathway for the current to pass at gate voltages far from the “threshold” voltage, changing the onset and ON/OFF currents of the device. Then you try to reduce the channel thickness, but, in silicon, the mobility rapidly decreases with thickness – besides the fact that it is also limited by the roughness you can achieve by your fabrication setups. If you can’t reduce the thickness, you can’t decrease the length without affecting the ON/OFF ratios and onsets of the device. You will also want your device onset to happen at the lowest possible gate voltages, and so you will want to use high-k dielectrics. Unfortunately large scale reliable uniform depositions of these materials are still technologically out of reach. If you can’t use better dielectrics, you could use channels that have higher mobility in order to have high ON currents using lower gate voltages (and source-drain bias); but higher mobility is associated with carriers with low effective mass, which then promotes tunneling between the source and drain. It seems then that you are as limited by your fabrication technology as by the materials you are using.

It happens that in 2004, using a simple scotch tape and armed with patience, it was possible to manually exfoliate a stable-at-environmental-conditions one atom thick continuous layer of graphite from a bulk sample, called graphene. The keywords here are “one atom thick”, “continuous”, and “stable”. After realizing that this method could be employed on virtually any van der Waals solid, quickly other layered materials were isolated in its two dimensional form: molybdenum disulfide, tungsten diselenide, and other transition metal dichalcogenides (TDMCs). Figure 3 depicts the core elements for exfoliating graphene (or TDMCs).

Figure 3 – a) All you need to fabricate one atom thick layers of graphite: commercially available double sided scotch tape, bulk graphite, and a substrate (not shown in this figure, but with a suitable thickness for optical contrast). b) Random PhD student exfoliating.

These two dimensional electron gases manifest a wide range of properties, from the gapless high mobility graphene, to the lower mobility but higher band gap molybdenum disulfide (MoS2), the superconducting niobium disulfide, and the dielectric boron nitride.

Suddenly, you could reach the ultimate thinness limit with an easy process, making it quickly and readily available to the research community, and providing the electronic industry the first glimpse on electronics based on 2D materials. Stacking them laterally or vertically, heterostructures composed of many layers could be devised to test its applications and search for new physics. As an example, you could use graphene to contact MoS2 field effect transistors, and encapsulate it with boron nitride to keep the channel clean and isolated, while working as a gate dielectric and as a scattering suppresser. Over the years, many optoelectronic and electronic applications were demonstrated.

But 2D materials did not come only as another range of materials to be used in electronics.  They provide a rich platform for fundamental physics. Many theoretical frameworks predicted a wide range of phenomena, from spin and inverse Spin Hall Effect, Quantum Anomalous Hall Effect, valley dependent transport, quantum oscillations, weak and weak-anti localization, superconductivity, among others. Based on them, several new fields emerged, making use of properties that do not play a role in conventional electronics systems, as spin-orbit coupling and berry phase, but are enablers for spintronics, spin-orbitronics, and valleytronics applications. Some might argue that there is no novelty in the physics they provide, as all these concepts were already conceived, described, and some confirmed in the past. Still, the questions that holds is “what happens to all these phenomena when you scale them down to its minimum thickness?”. After all, we are speaking of structural confinement to its limit. It can’t get any thinner than this.

You could point out other arguments that justify its success, but, in the end, 2D materials paved its path for both researchers and industry by supplying a platform to fulfil their needs, be it new physics for the researchers, or as a solution for the ever continuous requirement of higher performing and optimized devices.

Check out the other posts on this blog and you will find more reasons for their success.